1. Field of Applicable Technology
The present invention relates to an image processor for processing data representing a source image, and in particular to a local image processor which executes processing of local image data representing successive sets of pixels extracted from the source image, and which is suitable for multiprocessor parallel operation.
2. Prior Art Technology
In the prior art, in order to achieve a high speed of processing of an image formed of an array of pixels, various methods of parallel processing have been proposed, i.e. in which data of a plurality of pixels are processed in parallel. The image processing can include such operations as spatial mathematical processing, non-linear approximation computations, etc. At present, the generally utilized method for parallel image processing is to employ a plurality of "local image" processors, each of which sequentially processes successive small "local images" from a source image, with these processors operating in parallel. Each local image consists of an array of pixels extracted from a pixel array which forms the source image. The larger the size of each local image, the more complex becomes the operation, and the advantage of increased speed of processing is difficult to achieve. In addition, since each local image processor must temporarily store local image data, large amounts of memory capacity are required if the local image size is made large.
For that reason, the local image size is set as a small array of m by n pixels (were m and n are fixed integers, for example each having the value 3). As successive local images are sequentially processed, the local image region is in effect repetitively moved across the source image by successive horizontal scans which are sequentially displaced vertically by one line of pixels.
Prior art examples of such local image processors which are relevant to the present invention are described for example by Mori et al in U.S. Pat. No. 4,845,767 and U.S. Pat. No. 4,791,677.
In the prior art, such local image processing has generally been used for example for operations in which each local image is processed and the results obtained are used to determine a condition (e.g. brightness level) of one corresponding pixel of an output image that is subsequently generated. In addition to the types of image processing operations mentioned above, such local image processing is also suitable for a wide range of processing including averaging operations, differentiation operations, data conversion, etc. Since the circuit scale can be made comparatively small, circuits for executing such local image processing have been increasingly implemented as LSI integrated circuit devices. However in the prior art, although such local image processors are available which can be connected for parallel multiprocessor operation in order to achieve a higher processing speed, this is only possible for a type of processing in which each of the local image processors executes an identical type of operation. To achieve multiprocessor operation when it is necessary for each local image processor to execute a different operation (as required in image feature abstraction, described hereinafter) it has been necessary to use specially designed dedicated processors, so that that prior art local image processors are lacking in flexibility of use.
FIG. 1 shows a prior art example of a local image processor, in which the local image region size is 3.times.3 pixels. The local image processor 10 includes a local image register 1, for holding the local image, which receives image signal data representing successive pixels. Specifically, the local image register 1 receives the image signal (i.e. generated by converting each of successive pixels of the source image into a corresponding set of n data bits, which are supplied as a parallel n-bit data signal constituting the image signal), the image signal delayed by one horizontal scanning line of the source image, and the image signal delayed by two horizontal scanning lines, i.e. the local image register 1 receives three sets of input signal lines. A program memory 3 serves to store a program for executing the local image processing, and is controlled by a program control circuit 4. To control the execution of local image processing, the program memory 3 also produces output signals for controlling operations of the local image register 1, a computation section 2 and the program control circuit 4. A clock signal control circuit 5 operates on the basis of input signals applied thereto, i.e. a system control signal, a program "start" signal, and a chip expansion signal, and controls the inputting of image signal data to the local image register 1, the outputting of computation results from the computation section 2, and also the operation of the program control circuit 4.
The local image processor 10 executes identical processing (determined by the contents of the program memory 3) on each set of local image data, and thereby obtains processing results based on all the pixels of the entire source image, which are outputted from the computation section 2.
FIG. 2 shows examples of operating waveforms of various sections of the local image processor 10 of FIG. 1. The local image register 1 consists of a set of three shift registers (which respectively receive as input signals the image signal, the image signal delayed by one horizontal scanning line of the source image, and the image signal delayed by two horizontal scanning lines) each shift register having a set of three shift register stages 6, with the output of each shift register stage 6 being supplied to a corresponding memory cell 7. The output data of each shift register stage 6 can be written into the corresponding memory cell 7 under the control of a memory write signal that is produced by the clock signal control circuit 5. A "shift" signal operation is executed by each of these shift registers in response to each pulse of a "shift" signal that is produced from the clock signal control circuit 5, with this "shift" signal being generated in synchronism with rising edges of the system clock signal that is also generated from the clock signal control circuit 5. That is, data for a new set of 3 pixels are shifted in parallel into the local image register 1, to configure a new local image, at each rising edge of the "shift" signal, and these local image data are written into the respective ones of the memory cells 7 on the next falling edge of the memory write signal, which is synchronized with the system clock signal.
The system clock signal is inputted to the clock signal control circuit 5 from an external source, to control the timings of overall operations of the local image processor. The clock signal control circuit 5 also generates a "program start" signal, which is synchronized with the "shift" signal and which functions to initiate processing operations by the local image processor. The clock signal control circuit 5 also receives a chip expansion signal, which is utilized when a plurality of such local image processors are to be operated together. The "shift" signal from the clock signal control circuit 5 is generated based on the "start" signal and the system clock signal, and goes to the high logic level (referred to in the following as the "H" level) on the rising edge of the first system clock signal pulse to occur after the "program start" signal goes to the "H" level, and returns to the low logic level (hereinafter referred to as the "L" level) on the next falling edge of the system clock signal. The "shift" signal is controlled in accordance with the state of the chip expansion signal, such as to be inhibited when the chip expansion signal is at the "H" level, as shown in FIG. 2. An "output enable" signal is produced based on the "start" signal and the chip expansion signal.
As described above, data are normally shifted into the local image register 1 at each rising edge of the "shift" signal from the clock signal control circuit 5. At this time, if the chip expansion signal is at the "L" level, the memory write signal also goes to the "H" level, and the new image data are stored into the memory cells 7, while at the same time the "start" signal produced from the clock signal control circuit 5 goes to the "H" level. The "start" signal is supplied to the program control circuit 4, which is thereby reset to produce an initial address value for the program memory 3, and the address values generated by the program control circuit 4 are thereafter successively determined by the condition signal from the computation section 2, in successive periods of the system clock signal. In response to each address value supplied thereto from the program control circuit 4, the program memory 3 outputs command signals etc. in accordance with the program contents corresponding to that address, which are supplied to the local image register 1, the computation section 2 and the program control circuit 4 as shown in FIG. 1. The contents of specific ones of the memory cells 7 are thereby transferred to the computation section 2, and processing executed thereon by the computation section 2, in accordance with the program contents of the program memory 3. The sequence of address values that are outputted from the program control circuit 4 can be modified in accordance with the program contents, or can be modified in accordance with results obtained during processing (by the condition signal supplied from the computation section 2 to the program control circuit 4). In this way the program can execute jump operations.
When the "output enable" signal from the clock signal control circuit 5 goes to the "H" level, the operational results that have been obtained are outputted from the computation section 2. If the chip expansion signal goes to the "H" level, then the "output enable" signal is held at the "L" level, and the data outputs of the computation section 2 are held at the "L" level.
It is possible to utilize a plurality of such prior art local image processors functioning together, by means of the chip expansion signal, to form a parallel processing system which can provide a higher speed of image processing than is possible with a single local image processor. This will be described referring to FIG. 3, which is a block circuit diagram illustrating two of such local image processors connected to operate in parallel. FIG. 4 is a corresponding waveform diagram, for describing the operation. In FIG. 3, each of the local image processors 10a, 10b, is coupled to receive as input signals the image signal, the image signal delayed by one horizontal scanning line of the source image, and the image signal delayed by two horizontal scanning lines, together with the system clock signal and the "program start" signal. In addition, the "program start" signal is transferred through a divide-by-two frequency divider circuit 11, and resultant output signals are supplied as a chip expansion signal to each of the local image processors 10a and 10b, so that the respective chip expansion signals that are supplied to the local image processors 10a, 10b will mutually differ in phase by 180.degree.. The operational results that are produced from the local image processors 10a, 10b are combined in an OR gate 12, and outputted therefrom.
New data are written into the memory cells 7 of a local image processor 10a or 10b only when the chip expansion signal that is applied to that local image processor is at the "L" level. As a result, as illustrated in FIG. 4, input data shifts occur for local image processor 10a in the (n-4).sup.th, (n-2).sup.th, n.sup.th, . . . periods of the input image signal, with subsequent processing outputs being correspondingly indicated as the "processing output (a)", while input data shifts occur for local image processor 10b in the (n-3).sup.th, (n-1).sup.th, (n+1).sup.th, . . . periods of the input image signal, with subsequent processing outputs being correspondingly indicated as the "processing output (b)". Thus in effect the local image processors 10a and 10b are processing in parallel two streams of local images, with the resultant processing results being combined in the OR gate 12 to obtain the final output results.
It is thus possible to combine a plurality of prior art local image processors of the type described above, to obtain a higher processing speed than is possible with a single local image processor. However such a prior art processor has various disadvantages. Since the only input information that is available to the processor during operation is the local image data, with no information being available concerning the location of a specific local image within the source image, it is not possible to vary the processing of a particular local image in accordance with the position of that local image within the source image. Furthermore when a plurality of successive source images are sequentially processed (e.g. successive frames or fields of a video signal) there is no information available to the local image processor to indicate the position, within that sequence of source images, of the source image which is currently being processed. Thus, it is not possible for the program stored in the program memory 3 to vary the processing that is applied to each source image (or to specific pixels of each source image) in accordance with the position of the source image within a sequence of source images. It is therefore not possible to execute, as a very simple example, such basic image processing operations as gradual fade-out of a video image that is generated from the output results.
In addition, with the type of image processing described above, each of successive local images is processed (during parallel operation of two or more local image processors) in an identical manner. The results of processing each local image are then generally used to determine a condition of a corresponding pixel of an output image that is generated based on the processing results.
However there is a type of image processing in which specific parameters of one or more regions within the source image (such as the total area, length of boundary, center position, etc.) are measured. This is required for example when data of an image showing a workpiece are to be utilized to control an industrial robot, e.g. with information concerning the position, shape etc. of the image region corresponding to the workpiece being obtained as the processing results. In order to achieve a sufficiently high speed of processing, it is preferable to execute two or more types of processing in parallel on each local image, e.g. to obtain area information and boundary length information etc. at the same time. It has not been possible to execute this type of multiprocessor operation with a prior art local image processor such as that described above.
For these reasons, such a prior art local image processor is lacking in flexibility and generality of application.
Moreover, although an enhanced processing speed can be obtained by connecting a plurality of such a prior art local image processors for operation together, the maximum processing speed that can be achieved is still not fully satisfactory for certain applications, and there is a requirement for a capability for achieving a higher processing speed. Specifically, intermediate computation results already obtained by one local image processor cannot be used in a computation which is being executed by another local image processor, so that large numbers of unnecessary computation steps are inevitable.
Further, if a plurality of such local image processors are to be formed upon a single integrated circuit chip, the problem arises that an excessively large number of circuit elements must be formed, due to the complex structure of each processor.